Embedded Tutorial 1

Title: Automotive embedded software architecture in the multicore age
Presenters: Massimo Violante (Politecnico di Torino - Italy), Paolo Gai (Evidence - Italy)
Session: 4C

Abstract: Multicore is a game changer for automotive, allowing consolidating heterogeneous applications into a single device with benefits in terms of cost and reuse. Multicore asks for: 

• Virtualization of applications, moving from the hardware-centric perspective to the function-centric perspective: applications on a single electronic control unit (ECU) are transformed into hardware-agnostic functionalities that hosted by multicore ECUs alongside other, unrelated, applications. The tutorial presents the technologies available to support this concept such as AUTOSAR and embedded virtualizations.
• The guarantee that different applications exposing different criticalities (e.g., ISO26262 ASIL D and ISO26262 ASIL B) can coexist. The tutorial addresses the main problems that have to solved discussing the state of the art.

Biography Massimo Violante: Massimo Violante received the MS and PhD from Politecnico di Torino, Italy, where he is now Associate Professor. Prof. Violante main research topics are the design and validation of embedded system for safety- and mission-critical applications, with particular emphasis on the use of commercial off-the-shelf components like multicore processors and field programmable gate arrays in automotive and avionic applications. Prof. Violante published more than 150 papers in the area of testing and designing reliable embedded systems, and he co-authored two books. He served as program co-chair and general co-chair of the IEEE Defect and Fault Tolerance in VLSI and Nanotechnology Systems for 2011 and 2012 and as Program Chair for the IEEE European Test Symposium for 2012. Prof. Violante is active in a number of research projects in the area of embedded systems for space, avionic and automotive applications in collaboration with European Space Agency, Thales Alenia Space, Magneti Marelli, CNH, FCA, GMPTE.

Biography Paolo Gai: Dr. Paolo Gai, CEO, graduated (cum laude) in Computer Engineering at University of Pisa in 2000 with a graduation thesis developed at the ReTiS Laboratory of the Scuola Superiore Sant’Anna on the development of the modular real-time kernel SHaRK. He obtained the PhD from Scuola Superiore Sant'Anna in 2004. Since 2000, he founded the ERIKA Enterprise project, an open-source RTOS which recently reached the OSEK/VDX certification, and which is currently used by various industries and universities. Since 2002 he is CEO and founder of Evidence Srl, a SME working on operating systems and code generation for Linux- and ERIKA- based industrial products in the automotive and white goods market. His research interests include development of hard real-time architectures for embedded control systems, multi-processor systems, object-oriented programming, real-time operating systems, scheduling algorithms and multimedia applications.

Embedded Tutorial 2

Title: Cell Aware and Stuck-Open Tests
Presenter: Adit Singh (Auburn University)
Session: 6A

Abstract: Cell Aware testing has received much publicity over the past couple of years, with several reported success stories in screening defects missed by traditional stuck-at and transition delay fault (TDF) testing. For example, at ITC 2012, Hapke et al. reported 885 DPPM test escapes in a 32 nm notebook processor part from industrial strength stuck-at and 5-detect TDF testing. This raises some important questions: What are these new defects that are being detected by cell aware tests? Why are they missed by traditional stuck-at and TDF testing? Why has this problem only recently been discovered? Can traditional cell unaware test generation be enhanced to detect these faults? This embedded tutorial presents a detailed study of the cell aware test generation methodology to answer these questions. Further, we show that many, although not all, of the faults uniquely detected by cell aware tests, can also be detected by explicitly targeting stuck-open faults in the circuit.

Embedded Tutorial Summary: Cell Aware testing has received much publicity over the past couple of years, with several reported success stories in screening defects missed by traditional stuck-at and transition delay fault (TDF) testing. For example, at ITC 2012, Hapke et al. reported 885 DPPM test escapes in a 32 nm notebook processor part despite industrial strength stuck-at and 5-detect TDF testing. Significant additional fallout from cell aware tests has also been reported for automotive parts already screened to stringent “zero-defect” standards. Importantly, the vast majority of these test escapes were observed to cause failure in actual system application, pointing to a serious field reliability issue. This raises some important questions: What are these new defects that are being detected by cell aware tests? Why are they missed by traditional stuck-at and TDF testing? For what applications are these test escapes a real problem? Why has this problem only recently been discovered? Can traditional cell unaware test generation be enhanced to detect these faults? This tutorial presents a detailed study  of the cell aware test generation methodology to answer these questions. The aim is to analyze and understand the defects in modern standard cell libraries missed by traditional tests but uniquely  covered by this new test approach which employs both single pattern “Stuck-At” tests, and two-pattern “Transition Pattern” tests. We correlate this analysis with the available defect detection statistics reported by published volume production studies of the Cell Aware test methodology. It has been observed that the vast majority, 80-90%, of the additional fallout from the Cell Aware tests results from the Transition Patterns. Furthermore, successful detection of these “transition” faults does not appear to be highly timing dependent. The Cell Aware Transition Patterns are primarily developed to target all open and resistive open defects in complex CMOS standard cells. These defects can require two pattern tests for reliable initialization and detection. A significant focus of the presentation will be on understanding which resistive opens in standard cell libraries remain undetected by traditional TDF timing tests. We will then generalize these observations to identify the specific layout locations (defect sites) in complex CMOS circuit structures that are commonly missed by TDF tests. This analysis will also provide guidance as to how traditional two-pattern test generation can be enhanced to cover many of these resistive open defects. It turns out that while many additional open defects, missed by TDF testing, can indeed be targeted by test generation using just the gate level netlist, ensuring the efficient detection of all TDF undetected opens necessarily requires cell layout information. We discuss the relative size of this defect coverage loss if layout information is not utilized. We further show why this loss of coverage grows with the number and size of the complex CMOS cells utilized by the design.

Biography: Adit D. Singh received the B.Tech from the Indian Institute of Technology (IIT) in Kanpur, and the M.S. and Ph.D. from Virginia Tech, all in Electrical Engineering. Currently he is James B. Davis Professor of Electrical and Computer Engineering at Auburn University. Earlier, he has held faculty positions at the University of Massachusetts, Amherst and Virginia Tech in Blacksburg. His research interests span high performance VLSI systems, IC and SOC testing, and microelectronic system reliability and fault tolerance. He has published extensively in these areas, and holds several international patents that have been licensed to industry. He is particularly recognized for his pioneering contributions to statistical methods in test and adaptive testing. In addition to extensive support from US the National Science Foundation, his research has also been supported by the Max Plank Society of Germany, and the Fulbright Foundation, the National Science Council of Taiwan, and the Government of India. He is a popular lecturer and over the years has been invited to present over seventy technical courses at international conferences, and in-house in companies. Professor Singh served two terms (2007-11) as Chair of the IEEE Test Technology Technical Council, and currently serves on the Board of Governors of the IEEE Council on Design Automation (CEDA), and on the editorial boards of IEEE Design and Test Magazine and the Journal of Test and Test Applications (JETTA). Over the years has held leadership positions in dozens of technical conferences, most recently serving on the steering committees of the International Test Conference (2008-2012), the VLSI Test Symposium (2001-2014), as Co-General Chair for the 2010-14 IEEE International Workshops on Reliability Aware Design and Test (RASDAT), and Co-Program Chair of the 2014 International Conference on VLSI Design. He is a Fellow of the IEEE, and a "Golden Core" member of the IEEE Computer Society.

Embedded Tutorial 3

Title: Practises in High Speed I/O Testing
Presenters: Salem Abdennadher (Intel Corporation - United States), Saghir Shaikh (Broadcom - United States)
Session: 6B

Abstract: This embedded tutorial presents the existing industrial techniques to meet the ever increasing test complexity of High Speed IO’s (HSIO). It first describes the basic design of both serial and parallel HSIOs and then presents various testing methods of HSIO, such as timing margining, voltage margining, compensation testing, leakage testing and etc. The examples of all these test methods will be presented with special emphasis on DFT and BIST based approaches of HSIO testing and their suitability to the production level environment.

Biography Salem Abdennadher: Salem Abdennadher, Technologist, Intel Corporation has seventeen years of experience in mixed-signal design and DFT. Soon after graduating with Masters from Oregon State University 1992, he joined the industry and has worked with a research lab in France, Motorola, Level One Communications and Intel. His recent publications and international patent filing in mixed signal DFT/BIST ranges from Filter BIST, On-chip Jitter BIST, to mixed signal behavioral modeling and noise extraction and prediction. Salem also has presented dozens of tutorials through TTEP at ATS’04, LATW’05, VTS’05, ITC’05, ITC’06, DATE’07, ETS’07, ITC’08, ITC’09, VTS’09, ITC’10, ITC’11. ITC’12, ITC’13 and ITC’15 and is an invited speaker for the ATS’05 industry challenges section.

Biography Saghir Shaikh: Saghir A. Shaikh, Ph.D., Senior Principal IC Design Scientist at the Mobile and Wireless Group at Broadcom Corporation in San Diego. A graduate of the University of Texas at Austin (96), Dr. Shaikh has seventeen years of industrial experience in DFT and has authored more than a dozen research papers which are presented in various conferences such as ITC, ICCAD, and VTS. Saghir also has presented ten tutorials through TTEP at ATS’04, LATW’05, VTS’05, ITC’05, ITC’06, DATE’07, ETS’07, ITC’07, ITC’08, ITC’09, VTS’09, ITC’10, ITC’11, and ITC’ 12 and was an invited speaker for the ATS’05 industry challenges section. Saghir has served as reviewer to ITC, VTS, and DAC and member Program Committee for 3D-Testing Workshop 2013, and TVHSAC’13 and VTS’14.

Embedded Tutorial 4

Title: Cross-layer Resilience 
Presenter: Subhasish Mitra(Stanford University, USA)
Session: 6C

Abstract: Resilience to hardware failures is essential for a large class of future computing systems that are constrained by the so-called power wall: from embedded systems to supercomputers. To overcome this major challenge, we advocate and examine a cross-layer resilience approach. Two major components of this approach are: 1. System- and software-level effects of circuit-level faults are considered from early stages of system design; and, 2. resilience techniques are implemented across multiple layers of the system stack – from circuit and architecture levels to runtime and applications – such that they work together to achieve required degrees of resilience in a highly energy-efficient manner. Illustrative examples to demonstrate key aspects of cross-layer resilience will be discussed.

Biography: Professor Subhasish Mitra directs the Robust Systems Group in the Department of Electrical Engineering and the Department of Computer Science of Stanford University, where he is the Chambers Faculty Scholar of Engineering. Before joining Stanford, he was a Principal Engineer at Intel. 

Prof. Mitra's research interests include robust systems, VLSI design, CAD, validation and test, nanosystems, and emerging neuroscience applications.  His X-Compact technique for test compression has been key to cost-effective manufacturing and high-quality testing of a vast majority of electronic systems, including numerous Intel products. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation tools. He, jointly with his students and collaborators, demonstrated the first carbon nanotube computer, and it was featured on the cover of NATURE. The US NSF presented this work as a Research Highlight to the US Congress, and it also was highlighted as "an important, scientific breakthrough" by the BBC, Economist, EE Times, IEEE Spectrum, MIT Technology Review, National Public Radio, New York Times, Scientific American, Time, Wall Street Journal, Washington Post, and numerous other organizations worldwide.

Prof. Mitra's honors include the Presidential Early Career Award for Scientists and Engineers from the White House, the highest US honor for early-career outstanding scientists and engineers, the ACM SIGDA/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation, "a test of time honor" for an outstanding technical contribution, the Semiconductor Research Corporation's Technical Excellence Award, and the Intel Achievement Award, Intel’s highest corporate honor.  He and his students published several award-winning papers at major venues: IEEE/ACM Design Automation Conference, IEEE International Solid-State Circuits Conference, IEEE International Test Conference, IEEE Transactions on CAD, IEEE VLSI Test Symposium, Intel Design and Test Technology Conference, and the Symposium on VLSI Technology. At Stanford, he has been honored several times by graduating seniors "for being important to them during their time at Stanford."

Prof. Mitra has served on numerous conference committees and journal editorial boards. He served on DARPA's Information Science and Technology Board as an invited member. He is a Fellow of the ACM and the IEEE.